KGP RISC Processor

About

In this project, I developed a 32-bit single-cycle processor for a given instruction set architecture (ISA). In addition to the instruction format, I designed the data path and control path elements including ALU, registers, branching mechanism, instruction fetch and memory. Subsequently, I implemented the design using Verilog and tested various programs like GCD, binary search and merge sort using a Nexys-4 FPGA. I also developed an assembler using C++ to obtain the binary codes of the programs written using the ISA.

Code

Source code of the project: Github Repository